Embodiments of the invention relate generally to the fabrication of semiconductor circuits and more particularly to the fabrication of hybrid semiconductor circuits comprising semiconductor devices with different semiconductor materials.
Silicon is the basic material for present solid-state electronics, and processing techniques have evolved for decades. Hence, most electronic integrated circuit devices are based on silicon.
However, III-V compound semiconductors, and especially InGaAs, are being considered as a potential alternative for replacing strained Si in the channel of future nFETs due to their remarkable electron mobility. Moreover, some III-V compound semiconductors present several advantages for opto-electronics applications when compared to Si.
A monolithic integration of compound semiconductors on silicon wafers is desirable and has extensively been investigated in the past. Several problems need to be overcome when compound semiconductors and conventional silicon technologies are combined. First, there is a large lattice mismatch between a crystalline silicon substrate and most compound semiconductor crystals. Further, there is a thermal expansion coefficient mismatch between the (silicon) wafer material and the active compound semiconductor material. Additionally, a structural mismatch between diamond-like structures and zincblende structures may occur. It is an overall goal to achieve high crystalline quality over various monolithic layers for compound semiconductor on a foreign substrate such as silicon.
In an effort to achieve high crystalline quality in crystalline material layers that show a lattice mismatch, several methods have been developed. For example, direct epitaxy of blanket layers allow for a gradual transition from one lattice parameter to the next. However, relatively thick transition layers are needed to reduce the defect density considerably.
Techniques to combine compound semiconductor materials with conventional silicon wafers include bonding techniques. In direct wafer bonding, a compound hetero structure is fabricated on a donor wafer wherein the donor wafer material is eliminated after bonding with the conventional silicon wafer. This makes the bonding technology relatively expensive. Further, bonding is limited to the size of costly compound substrate wafers.
Another approach for combining lattice-mismatched materials such as compound semiconductors with silicon substrates is the aspect ratio trapping approach. Aspect ratio trapping (ART) refers to a technique where crystalline defects are terminated at non-crystalline, for example dielectric, sidewalls.
It is desirable to provide improved fabrication methods for hybrid semiconductor circuits. In particular, techniques to integrate compound semiconductors such as III-V semiconductors on common Si substrates would be highly desirable.